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DGIST Upgrades the CMOS Standard Process Line

  • 조회. 457
  • 등록일. 2021.01.12
  • 작성자. External Relations Team

Expansion of the standard CMOS process line(0.5 μm) in Center for Core Research Facilities, DGIST

 

Researchers working on CMOS wafers
DGIST Researchers working on CMOS wafers



 The Center for Core Research Facilities in DGIST will upgrade its clean room that is capable of manufacturing complementary metal oxide semiconductors (CMOSs). DGIST, in particular, is planning to provide their facilities to schools and other research institutes, which is expected to help various research and development, such as the development of devices for next-generation semiconductors based on CMOS.

 

CMOS wafers
CMOS wafers

 

 The Center for Core Research Facilities has built an additional CMOS standard process line (0.5 μm) with the aim of enhancing research competence on Processor-In-Memory (PIM) and creating derivative values through the utilization of its semiconductor manufacturing processes. It has enabled the manufacturing of devices in batches rather than at the unit process level. The recent upgrade of the facility will be great help for semiconductor-related research and for education purposes; research device tests that are required to be driven at the CMOS level, provision of a platform for developing new semiconductor devices and materials based on CMOS, provision of CMOS wafers, and CMOS-based education programs.

 

Clean room located in the Center for Core Research Facilities
Clean room located in the Center for Core Research Facilities 

 

 The Center already built a high-level research platform capable of supporting semiconductor processing and nano-analysis, and is providing a batch service that enables material and device analysis and verification. The center, in particular, is equipped with a 6-inch-based clean room, and there are a total of 170 types of silicon-based semiconductor processing, MEMS and micro processing, communication devices, process equipment such as sensor and measurement simulator, and nano/bio analysis equipments. 

 “In order to cope with the expansion of the global foundry market and increasing needs for research and development in domestic industries, academia, and research, we have improved the CMOS standard process line,” said Bongho Lee, the director of the Center for Core Research Facilities. “The upgrade is expected to help research on the next-generation semiconductor technology conducted by various researchers as well as local companies.”

 On the other hand, the CMOS standard process line was jointly constructed by members of the DGIST Center for Core Research Facilities in cooperation with professors and researchers in the semiconductor field, and the mask design was shared by the Institute of Semiconductor Fusion Technology of Kyungpook National University.

 

The Center for Core Research Facilities, DGIST
The Center for Core Research Facilities, DGIST